Common electrode wire for plating

ABSTRACT

A common electrode line for plating for collectively forming conductive patterns of a plurality of circuit substrates on a main substrate, and for plating the conductive patterns of the plurality of circuit substrates at the same time by the common electrode lines for plating, wherein the common electrode lines for plating  22  respectively connected to pads  14  of the plurality of circuit substrates  20 A are formed on both front and back surfaces of the main substrate and connected via through holes  11 , the common electrode lines for plating are wired from the circuit substrate across a cut line which divides a substrate into the plurality of circuit substrates on any of the front and back surfaces.

TECHNICAL FIELD

[0001] The present invention relates to common electrode lines forplating for collectively forming a conductive pattern of a plurality ofcircuit substrates on a main substrate, e.g., common electrode lines forplating for collectively forming electrode pads and a conductive patternof a ball grid array (BGA) type semiconductor package circuit substrate.

BACKGROUND ART

[0002] In recent years, with becoming smaller and denser ofsemiconductor packages, a ball grid array (BGA) type semiconductorpackage that is flip chip bonded and wire bonded in which a bare chip isdirectly mounted facedown on a substrate has been developed.

[0003] Further, with emergence of a camera-integrated VTR, a cellulartelephone and the like, portable equipment having a small package whichhas substantially the same size as that of the bare chip, so-called CSP(chip size/scale package) have appeared. The development of the CSP hasbeen rapidly pursued and the demands of the market have been increased.

[0004] Technique of a conventional wiring substrate using a flexiblefilm for TAB is disclosed in Japanese Patent Application Publication No.7-66932. According to this technique, as shown in FIG. 1 of thispublication, in an electrical connection and short circuit frame in anetching wiring 4 for an integrated circuit, a lead wire 1 extending to aconnecting point 2 with respect to a wire of adjacent integratedcircuits is formed in a meandering manner. Therefore, by cutting betweenadjacent integrated circuits at a cutting position 7, the integratedcircuits can be divided without wasting material. As a result, all theshort circuit connections of the meandering pattern are separated bycutting at the cutting position 7, and the meandering pattern is formedas a terminal (lead wire) in the integrated circuit.

[0005]FIG. 10 is a partial plan view of adjacent chip circuits showingone pattern of another conventional common electrode line for platingdescribed in Japanese Patent Application Laid-open No. 9-55398.

[0006] In FIG. 10, in a semiconductor substrates 10, a plurality of chipcircuits are collectively formed on a same semiconductor substrate 10.The semiconductor substrate 10 comprises a silicon substrate, and is cutinto a predetermined size to divide into a large number of chipcircuits.

[0007] Common electrode lines for plating 12 are connected to electrodepads 14 of said each adjacent chip circuit 10A. The common electrodelines for plating 12 are meandering in a crank shape across cut lines Xand Y.

[0008] Wiring (conductive) patterns 13 of each chip circuit 10A areformed of the common electrode lines for plating 12.

[0009] The electrode pads 14 are disposed on an active surface side ofthe semiconductor substrate 10. Each electrode pad 14 is connected tothe corresponding wiring pattern 13 and functions as an externalconnecting electrode.

[0010] Each common electrode line for plating 12 has a predeterminedwidth, and meanders in the crank shape across the cut line X. Since thecommon electrode lines for plating 12 are formed on the same surface ofthe main substrate 10, a constant gap G1 is provided between the wiringpatterns 13 so that the adjacent common electrode lines for plating 12do not come into contact with each other.

[0011]FIG. 11 is an enlarged plan view of an essential portion showing apattern of another conventional common electrode line for plating. Thecommon electrode lines for plating 12 comprise a main line 12 asequentially formed between wiring patterns (conductive patterns), andbranch lines 12 b branched from the main line 12 a for connectingparticular pads (only a portion is shown in FIG. 11). In this case also,a constant gap G2 is provided between the wiring patterns 13 so thatadjacent common electrode lines for plating 12 (12 a, 12 b) do not comeinto contact with each other.

[0012] In these conventional techniques, the common electrode lines forplating 12 for short-circuiting pad patterns are provided before theelectrolytic plating processing and then, electrode material isdeposited on each pad pattern by the electrolytic plating processing toform a plurality of pad electrodes collectively. At the time of theelectrolytic plating processing, all the pad patterns have the sameelectric potential by the common electrode lines for plating 12, and adeposition amount and a film thickness of the electrode material of eachpad pattern are prevented from being varied. By forming the commonelectrode lines for plating 12 across the cut lines X and Y in ameandering manner, even if slight positional deviation of dicing isgenerated in a dicing step, it is possible to reliably (shut offconductively) cut the common electrode lines for plating 12, and shortcaused by short circuit of the common electrode lines for plating ineach chip circuit 10A is eliminated. Further, since the cutting width inthe dicing step is narrow, the chip circuit 10A can be cut and dividedwithout waste of the substrate material.

[0013] However, the above-described conventional common electrode linesfor plating have the following problems.

[0014] That is, the common electrode lines for plating 12 are formedsuch as to meander in the crank shape across the cut line. Each commonelectrode line for plating 12 has a predetermined width and is formed onthe same surface of the main substrate. Therefore, it is necessary toprovide predetermined gaps G1 and G2 between the wiring patterns 13 and13 so that the adjacent common electrode lines for plating, or thecommon electrode line for plating and the wiring pattern (conductivepattern) do not come into contact with each other. Thus, the number ofterminals (the number of pins) formed per one side of the circuitsubstrate is limited, and it is difficult to form the terminals at highdensity.

[0015] Even if the shape of the common electrode lines for plating ischanged from the crank shape into an inclined shape, it is difficult toincrease the number of terminals by the same reason.

[0016] Thereupon, it is an object of the present invention to providehigh reliable common electrode lines for plating of a main substrate inwhich the waste of substrate material at the time of dicing iseliminated, the gap between the wiring patterns is narrowed as small aspossible, the number of terminals per one side of each circuit substrateis increased, and the terminals can be formed at high density.

DISCLOSURE OF THE INVENTION

[0017] To achieve the above object, the present invention providescommon electrode lines for plating for collectively forming conductivepatterns of a plurality of circuit substrates on a main substrate, andfor plating the conductive patterns of the plurality of circuitsubstrates at the same time by the common electrode lines for plating,wherein the common electrode lines for plating respectively connected topads of the plurality of circuit substrates are formed on both front andback surfaces of the main substrate and connected via through holes eachother, and on any of the front and back surfaces of the main substrate,the common electrode lines for plating are wired from the adjacentcircuit substrates across a cut line which divides a substrate into theplurality of circuit substrates.

[0018] At that time, it is preferable that the common electrode line forplating is formed such as to meander along the cut line.

[0019] More specifically, the common electrode line for plating foralternately and continuously connecting through holes in adjacent twocircuit substrates is formed on the front surface of the substrate as amain line, and the other common electrode lines for plating which arebranched from the main line and connected to a particular pads areformed on the back surface of the substrate as branch lines.

[0020] Preferably, the common electrode line for plating for alternatelyand continuously connecting through holes in adjacent two circuitsubstrates is formed on the back surface of the substrate as a mainline, and the other common electrode lines for plating which arebranched from the main line and connected to particular pads are formedon the front surface of the substrate as branch lines, and vice versa.

[0021] According to the common electrode line for plating of the presentinvention having the above construction, each adjacent circuit substrateis divided without wasting the substrate material. Further, even if adistance between the conductive patterns is narrowed, each circuitsubstrate is reliably divided without generating short circuit by thecommon electrode lines for plating formed on the front and back surfacesof the main substrate. As a result, the number of terminals of thecircuit substrate is remarkably increased, and it is possible to providea highly density circuit substrate required in the market.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022]FIG. 1 shows one pattern example of a common electrode line forplating of the present invention formed on a main substrate on the sideat which an IC is mounted;

[0023]FIG. 2 shows one pattern example of a common electrode line forplating appearing on the main substrate shown in FIG. 1 on the side atwhich soldering bumps are formed;

[0024]FIG. 3 is an enlarged view of a portion E surrounded by dot-dashlines in FIG. 2;

[0025]FIG. 4 is an enlarged view of an essential portion in FIG. 3;

[0026]FIG. 5 is an enlarged view showing; in the same manner as FIG. 3,another pattern example of the common electrode line for plating of theinvention;

[0027]FIG. 6 is an enlarged view of an essential portion in FIG. 5;

[0028]FIG. 7 is an enlarged view showing; in the same manner as FIG. 3,another pattern example of the common electrode line for plating of theinvention;

[0029]FIG. 8 is an enlarged view of an essential portion showing; in thesame manner as FIG. 4, another pattern example of the common electrodeline for plating of the invention;

[0030]FIG. 9 is an enlarged view of an essential portion showing; in thesame manner as FIG. 4, another pattern example of the common electrodeline for plating of the invention;

[0031]FIG. 10 is a partial plan view of a circuit substrate showing apattern example of a conventional common electrode line for plating; and

[0032]FIG. 11 is an enlarged view of an essential portion in a patternexample of another conventional plating electrode line.

BEST MODE FOR CARRYING OUT THE INVENTION

[0033] The present invention will be explained in detail based on theaccompanying drawings.

[0034] In FIGS. 1 and 2, a main substrate 20 is cut and divided into aplurality of (four, in the drawings) circuit substrates 20A. On a frontsurface of each circuit substrate 20A, IC connecting bonding patterns 24are radially disposed in correspondence with pad electrodes (not shown)of an IC chip 21. The bonding pattern 24 is wire bonded to the padelectrode of the IC chip 21.

[0035] A plurality of through holes 11 are formed along cut lines X andY on a peripheral edge of each circuit substrate 20A. Common electrodelines for plating 22 comprise electrode lines 22A formed on the mainsubstrate 20 on the side (front surface) at which soldering bumps thatare external connecting conductive pattern of the main substrate 20 areformed, and electrode lines 22B formed on the main substrate 20 on theside (back surface) at which electronic component is mounted. The commonelectrode lines for plating 22A and 22B are connected to each other viathe through hole 11, and meander as a whole across the cut lines X and Yfor dividing the circuit into the respective circuit substrates 20A.

[0036] In FIGS. 1 and 2, the common electrode line for plating 22Aintersects the cut line X at right angles, the common electrode line forplating 22B is inclined with respect to the cut line X, the commonelectrode line for plating 22A is inclined with respect to the cut lineY, and the common electrode line for plating 22B intersects the cut lineY at right angles. The common electrode lines for plating 22A and 22Bare connected to the IC connecting bonding pattern in FIG. 1, and areconnected to a conductive patterns 13 which are connected to thesoldering ball pads 14. That is, the common electrode lines for plating22A and 22B formed adjacently are formed on front and back surfaces ofthe circuit substrate 20A across the cut lines. By continuouslyconnecting the common electrode lines for plating 22A and 22B throughthe through hole 11, the entire common electrode lines for plating forma common electrode line for plating meandering across the cut lines Xand Y.

[0037]FIG. 3 shows a portion E surrounded by dot-dash lines in FIG. 2.FIG. 4 is an enlarged view of an essential portion of FIG. 3.

[0038] The through holes 11 are formed on peripheral edges of eachcircuit substrates 20A constituting the main substrate 20 atpredetermined pitch and predetermined size along the cut lines X and Y.The common electrode lines for plating 22A and 22B are formed in ameandering manner across the cut lines X and Y on front and backsurfaces of the main substrate 20, and have predetermined widths.Therefore, a gap G3 is provided between conductive patterns 13 so thatthe adjacent conductive patterns 13 do not come into contact with eachother. However, since the common electrode lines for plating 22A and 22Bare separately formed on the front and back surfaces of the mainsubstrate 20, the conductive pattern 13 and the common electrode linefor plating 22B do not come into contact with each other, and the gap G3can be narrowed as close as possible. With this design, the number ofterminals per one side of the circuit substrate 20A can be increased.For example, in the case of the one example shown in FIG. 3, 13terminals can be formed per one side of the circuit substrate 20A, butin the case of the above-described conventional example (FIG. 10), onlynine terminals can be formed. According to the present invention, thenumber of the terminals per one side is greater than the conventionalexample by four and thus, the number of terminals in four sides of thecircuit substrate 20A is four times greater than the conventionalexample, i.e., greater than the conventional example by 16, and thehigher density can be realized.

[0039] Here, as shown in FIG. 4, through holes on one circuit substrateare allocated with odd-numbered, and through holes on the other circuitsubstrate are even-numbered, the common electrode line for plating 22Afor connecting from the odd-numbered through hole 11(1) to even-numberedthrough hole 12(2) is formed on the front surface of the main substrate20, and the common electrode line for plating 22B for connecting fromthe even-numbered through hole 11(2) to the odd-numbered through hole11(3) is formed on the back surface of the main substrate 20.

[0040]FIG. 5 is an enlarged view of another pattern example of thecommon electrode line for plating of the present invention.

[0041] The common electrode lines for plating shown in FIG. 5 comprise acommon electrode line for plating 22A functioning as a main line 22 aand common electrode lines for plating 22B functioning as branch lines22 b. The common electrode line for plating 22A connects a plurality ofthrough holes 11 on the front surface of the main substrate 20. Thecommon electrode lines for plating 22B are branched from the commonelectrode line for plating 22A via the through holes 11 and connected toinner pads 14 a disposed inside the circuit substrate 20A.

[0042]FIG. 6 is an enlarged view of an essential portion of FIG. 5. Eachthe common electrode line for plating 22A functioning as a main line 22a meanders in the crank shape across the cut line X, and alternatelyconnects through holes 11 provided in adjacent circuit substrates 20A.

[0043] Each the common electrode line for plating 22B functioning as thebranch line 22 b is connected to an inner pad through hole 11 a of theadjacent circuit substrate 20A across the cut line X, and is againbranched therefrom bypassing the adjacent circuit substrate 20A, and isconnected to an inner pad through hole 11 b of its own circuit substrateacross the cut line X.

[0044] Since the common electrode lines for plating are wired in such apattern, it is possible to remarkably narrow the gap G4 between theconductive patterns 13 as compared with the gap G2 of conventionaltechnique while keeping the same function as that of the conventionaltechnique shown in FIG. 11.

[0045] Although the main line 22 a is formed on the front surface of themain substrate 20 and the branch lines 22 b are formed on the backsurface of the main substrate 20 in the common electrode lines forplating shown in FIGS. 5 and 6, the main line 22 a may be formed on theback surface of the main substrate 20 and the branch lines 22 b may beformed on the front surface of the main substrate 20.

[0046]FIG. 7 is an enlarged view of another pattern example of thecommon electrode line for plating of the present invention. In thecommon electrode line for plating in FIG. 7, main lines 22 a eachcontinuously connecting a plurality of through holes 11 provided inadjacent circuit substrates 20A and 20A are formed on both front andback surfaces of the main substrate 20 alternately. That is, each commonelectrode line for plating 22A as a main line 22 a is straightly formedacross the cut line X on the front surface of the main substrate 20, andeach common electrode line for plating 22B as a main line 22 a is formedacross the cut line X in the crank shape on the back surface of the mainsubstrate 20.

[0047]FIG. 8 is an enlarged view of another pattern example of thecommon electrode line for plating of the present invention. The commonelectrode line for plating in FIG. 8 is a modification of the patternexample shown in FIG. 6. In this pattern example, the main line 22 ameandering in the crank shape across the cut line X is alternatelyformed on the front and back surfaces of the main substrate 20 throughthe through holes 11. The branch lines 22 b are formed on the surfacesopposite from the main line 22 a through the through holes 11.

[0048]FIG. 9 is an enlarged view of another pattern example of thecommon electrode line for plating of the present invention. The commonelectrode line for plating in FIG. 9 is also a modification of thepattern example shown in FIG. 6. In this pattern example, the main line22 a meandering in the crank shape across the cut line X is irregularlyformed on the front and back surfaces of the main substrate 20. Thebranch lines 22 b are formed on the surfaces opposite from the main line22 a through the through holes 11 in this case also.

[0049] The pattern shape of the common electrode lines for plating andpositional relation between the main line and the branch lines are notlimited to those described in the above embodiment, and variousmodifications are possible. Although all the common electrode lines forplating in the above embodiment are formed on the front and backsurfaces in a staggered format, the present invention is not limited tothis, and the common electrode lines for plating of the invention may bemixed with the common electrode line for plating meandering on only onesurface of the circuit substrate as shown in the conventional technique.

[0050] As described above, the common electrode lines for plating 22 (22a, 22 b) for establishing short circuit in a pad pattern are formedbefore the electrolytic plating processing, electrode material isdeposited on each pad pattern by the electrolytic plating processing tocollectively form a plurality of pad electrodes. As a result, at thetime of electrode plating processing, all the pad patterns are at thesame electric potential by the common electrode line for plating 22, anda deposition amount and a film thickness of the electrode material ofeach pad pattern are prevented from being varied. By forming the commonelectrode line for plating 22 across the cut lines X and Y in ameandering manner and carrying out the dicing, even if slight positionaldeviation of dicing is generated in a dicing step, it is possible toreliably cut the common electrode line for plating 22. As a result,short caused by short circuit of the common electrode line for platingin each chip circuit is eliminated. Further, since the cutting width inthe dicing step may be narrow, the chip circuit can be cut and dividedwithout waste of the substrate material.

[0051] Industrial Applicability

[0052] The present invention can effectively utilized as a circuitsubstrate having electronic components at high density, and theinvention can preferably be used for small portable equipment, e.g..electronic clock and communication equipment.

What is claimed is:
 1. A common electrode line for plating forcollectively forming conductive patterns of a plurality of circuitsubstrates on a main substrate, and for plating the conductive patternsof the plurality of circuit substrates at the same time by the commonelectrode lines for plating, wherein said common electrode lines forplating respectively connected to the conductive patterns of saidplurality of circuit substrates are formed on both front and backsurfaces of said main substrate and connected each other via throughholes, and on any of the front and back surfaces of the main substrate,said common electrode lines for plating are wired from adjacent circuitsubstrates across a cut line which divides a substrate into saidplurality of circuit substrates.
 2. A common electrode line for platingaccording to claim 1, wherein said common electrode line for platingwhich is formed on the front and/or back surface of said main substrateand which connects said through holes of said circuit substrate witheach other is wired from adjacent circuit substrates across said cutline.
 3. A common electrode line for plating according to claim 1 or 2,wherein said common electrode line for plating is formed such as tomeander along said cut line.
 4. A common electrode line for platingaccording to any one of claims 1 to 3, wherein when n-number of throughholes are formed on adjacent two circuit substrates in total, saidcommon electrode line for plating which connect first through hole ton-th through hole with each other in arbitrary combination is wired fromthe adjacent circuit substrate across said cut line, and at least onecommon electrode line for plating is formed on the back surface of thesubstrate.
 5. A common electrode line for plating according to claim 4,wherein when odd-numbered through holes are formed on one circuitsubstrate and even-numbered through holes are formed on the othercircuit substrate, said common electrode line for plating for connectingthe odd-numbered through hole and the even-numbered through hole isformed on a front surface of the substrate, and said common electrodeline for plating for connecting the even-numbered through hole and theodd-numbered through hole is formed on a back surface of the substrate.6. A common electrode line for plating according to any one of claims 1to 5, wherein said common electrode line for plating has another commonelectrode line for plating which is branched.
 7. A common electrode linefor plating according to any one of claims 1 to 5, wherein said commonelectrode line for plating has another common electrode line for platingbranched from said through hole.
 8. A common electrode line for platingaccording to claim 6 or 7, wherein said other common electrode line forplating meanders across said cut line.
 9. A common electrode line forplating according to any one of claims 6 to 8, wherein said other commonelectrode line for plating is formed on an opposite surface of thesubstrate on which said common electrode line for plating is formed. 10.A common electrode line for plating according to any one of claims 6 to9, wherein said other common electrode line for plating is connected tosaid conductive patterns formed on the front and back surfaces of saidcircuit substrate via said through hole.
 11. A common electrode line forplating according to any one of claims 6 to 10, wherein said othercommon electrode line for plating connects through holes to each otherdisposed on the opposite sides with respect to said cut line.
 12. Acommon electrode line for plating according to any one of claims 6 to11, wherein said common electrode line for plating for alternately andcontinuously connecting through holes in adjacent two circuit substratesis formed on the front surface of said substrate as a main line, andsaid other common electrode line for plating which is branched from saidmain line and connected to a particular pad is formed on the backsurface of said substrate as a branch line.
 13. A common electrode linefor plating according to any one of claims 6 to 11, wherein said commonelectrode line for plating for alternately and continuously connectingthrough holes in adjacent two circuit substrates is formed on the backsurface of said substrate as a main line, and said other commonelectrode line for plating which connect a through hole to a particularthrough hole is formed on the front surface of said substrate as abranch line.
 14. A common electrode line for plating according to anyone of claims 6 to 11, wherein said common electrode line for platingfor alternately and continuously connecting through holes in adjacenttwo circuit substrates is formed on the front or back surface of saidsubstrate arbitrarily as a main line, and said other common electrodeline for plating which connect a through hole to a particular throughhole is formed on an opposite surface of substrate on which said mainline is formed as a branch line.
 15. A common electrode line for platingaccording to any one of claims 1 to 14, wherein said common electrodeline for plating for connecting two or more pads or through holes in onecircuit substrate is bypassed the adjacent circuit substrate across saidcut line.
 16. A common electrode line for plating according to any oneof claims 1 to 14, wherein said conductive pattern formed on the frontsurface of said circuit substrate is an electrode pattern to beconnected to an electronic component, and said conductive pattern formedon the back surface is an electrode pattern to be connected to outside.